1. Field of the Invention
The present invention relates to a video signal synchronizing apparatus applicable to a video signal processing instrument having an expansion slot.
2. Description of the Related Art
A personal computer usually has at least one expansion slot for detachably connecting an expansion module to the personal computer in order to enhance a faculty of the personal computer. In a television camera system particularly for broadcasting use, there has been required to provide an expansion slot for connecting an expansion module such as noise compression module special video effect module. However, bringing such a requirement to completion could not be satisfied easily. This is due to a fact that in the television camera system, a time lag required for processing a video signal by an expansion module could not be ignored.
In a television camera system for business use or broadcasting use, it is sometimes required to synchronize the relevant television camera system with another video processing instruments such as television camera system and video recording and reproducing system. Such a synchronization is generally called a generator locking (GEN-Lock). Therefore, when an expansion module is connected to the television camera system, the GEN-Lock has to be performed by considering a time lag introduced by the expansion module. In general video cameras and video tape recorders for private use or domestic use, it is not necessary to take the GEN-Lock, and thus a time delay due to an expansion module including a video processing circuit dose not cause any problem. However, in the video processing instruments for business use or broadcasting use, the GEN-Lock is strictly required for synchronizing output video signals with an external reference signal, and when an expansion module having a time delay is added, a predetermined GEN-Lock could not be attained.
FIG. 1 is a block diagram showing a known GEN-Lock apparatus applied to a television camera system. There are provided a video signal generator 50 for generating a video signal, a video signal processing circuit 10, a synchronizing signal (sync-signal) separating circuit 20 for separating a synchronizing signal from an external reference signal (VBS/B13S), and a PLL (phase-lock loop) circuit 40 for generating a reference control signal whose phase is locked with the external reference signal. In this example, the PLL circuit 40 generates a horizontal driving signal whose phase is locked with a horizontal synchronizing signal HD supplied from the synch-signal separating circuit 20. The GEN-Lock apparatus further comprises an expansion module 30, which may be detachably connected to an expansion slot provided on an output side of the video processing circuit 10.
The expansion module 30 comprises a video processing circuit 31 for further processing an output video signal from the video processing circuit 10.
The PLL circuit 40 includes a phase detector or comparator 41, a low pass filter 42; a voltage controlled oscillator 43, a frequency synthesizer 44 and a phase adjusting circuit 45, these units being connected to constitute a loop. The frequency synthesizer includes a counter for counting a signal from the voltage controlled oscillator 43 and decoder for producing pulses at predetermined count values of the counter. In the present specification, such pulses are termed as a reference control signal. The reference control signal generated by the frequency synthesizer 44 is supplied to the video processing circuit 10, and the video processing circuit operates at timings controlled by the reference control signal. In the video signal generator 50, an optical image formed by a camera lens 60 is made incident upon an image sensing element 51 and is converted into a video signal. The image sensing element 51 is driven by a driving circuit 52, The thus converted video signal is outputted from the video signal generator 50 The driving circuit 52 is directly or indirectly controlled by the reference control signal A supplied from the frequency synthesizer 44. Therefore, the video signal supplied to the video processing circuit 10 is synchronized with the reference control signal A.
In the video processing circuit 10, from the reference control signal A there are formed various pulses such as clamping pulse and blanking pulse. In general, the reference control signal A includes the horizontal driving signal HD and vertical driving signal VD, and these driving signals are supplied on separate transmission lines or on a common transmission line as a composite signal.
The clamping pulse, blanking pulse and other pulses required for the video processing may be directly supplied from the frequency synthesizer 44 to the video processing circuit 10. In the following explanation, it is assumed that the horizontal and vertical driving signals HD and VD are supplied from the frequency synthesizer 44 to the video processing circuit 10.
At first, the horizontal synchronization will be explained. The operation of the PLL circuit 40 has been well known in the art, and therefore its explanation is dispensed with here, Furthermore, for the time being, the expansion module 30 is not connected to the expansion slot, and thus the video signal Q generated from the video processing circuit 10 is supplied to an output terminal as a finally processed video signal.
As explained above, the frequency synthesizer 44 generates the reference control signal A which is supplied to the video signal generator 50 and video processing circuit 10. The frequency synthesizer 44 further generates a signal having a horizontal period, and this signal is supplied via the phase adjusting circuit 45 to the phase comparator 41 to which is also supplied the horizontal driving signal HD extracted by the synch-signal separating circuit 20. Then, the phase comparator 41 produces a phase difference between these signals having the horizontal period. The PLL circuit 40 operates to make this phase difference to be zero, and a phase of the finally obtained video signal Q is synchronized with a phase of the external reference signal P.
Next, the vertical synchronization will be briefly explained with reference to timing charts shown in FIGS. 2A-2E.
Now it is assumed that a horizontal phase of the finally obtained video signal Q has been locked with a phase of the external reference signal (BBS) P, but these vertical phases are deviated from each other. FIGS. 2A and 2B represent a phase relationship between the external reference signal P and an output signal from a low pass filter (not shown) provided in the sync-signal separating circuit 20. When the output of this low pass filter (LPF) becomes lower level, a vertical reset pulse V.sub.reset is generated in synchronism with the horizontal synchronizing signal as depicted in FIG. 2C. Here, the vertical synchronizing signal (V-sync) has a period of H4-H7. It should be noted that the actual external reference signal P is different from that shown in FIG. 2A, but for the sake of explanation, it is simplified. Other signals are also simplified. Furthermore, in FIG. 2, the equivalent pulse is not shown, because this pulse is irrelevant to the GEN-Lock operation.
When the vertical reset signal V.sub.reset is generated by the sync-signal separating circuit 20 as shown in FIG. 2C, the counter provided in the frequency synthesizer 44 is reset and the frequency synthesizer starts to produce horizontal driving pulses H5, H6, H7--as illustrated in FIG. 2D. In this manner, the horizontal and vertical phases of the reference control signal A supplied from the frequency synthesizer 44 are locked with those of the external reference signal P, and therefore the phase of the video signal Q supplied from the video processing circuit 10 is locked with the external reference signal P.
The video signal supplied to the video processing circuit 10 is processed to be synchronized with the reference control signal A, from the PLL circuit 40. When no expansion module is connected to the expansion slot, a connection board which merely transmits the video signal without a time delay is inserted into the expansion slot.
FIGS. 3A-3F show waveforms of various signals. FIG. 3A illustrates the external reference signal P supplied to the sync-signal separating circuit 20, FIG. 3B represents the output signal Q supplied from the video processing circuit 10, and FIG. 3C illustrates the finally obtained video signal R supplied from the video processing circuit 31 provided in the expansion module 30 to the output terminal. When the video processing circuit 31 provided in the expansion module 30 does not introduce a time delay, a phase of the video signal Q generated by the video processing circuit 10 is identical with that of the finally obtained video signal R. However, when the video processing circuit 31 in the expansion module 30 has a time delay, a phase of the finally obtained video signal R' supplied from the video processing circuit 31 of the expansion module 30 is delayed by the delay time T.sub.D as shown in FIG. 3D. Therefore, the output video signal R' from the video processing circuit 31 of the expansion module 30 is delayed by the delay time T.sub.D with respect to the external reference signal P.
FIG. 3E shows the horizontal driving signal HD supplied from the sync-signal separating circuit 20 and FIG. 3F illustrates the reference control signal A generated by the frequency synthesizer 44.
In order to make a phase of the finally obtained video signal R' from the video processing circuit 31 of the expansion module 31 identical with a phase of the external reference signal P, it is necessary to adjust the phase adjusting circuit 45 in the PLL circuit 40 such that a phase of the reference control signal A is advanced by the delay time T.sub.D. If the delay time T.sub.D is large, the phase adjusting circuit 45 has to be constructed to have a wide phase adjusting range. Therefore, the phase adjusting circuit 45 becomes complicated and large.
Moreover, when the presently used expansion module 30 is replaced by another expansion module having a delay time different from that of the presently used expansion module, it is necessary to readjust the phase adjusting circuit 45. This phase adjusting operation is rather cumbersome and requires an experienced skill,